Get updates about new events(Free)
Webinar Calendar
- Sun
- Mon
- Tue
- Wed
- Thu
- Fri
- Sat
Category search
Webinar Help
- Registering in advance to participate in the Webinar
- Updating your personal information
- Participating in the Webinar
- Setting up your computer to join the Webinar
- Why is it difficult to enter the seminar after it started
- Why can't I log in the seminar
Q&A
Homepage / Q&A
Signal Conditioning for Backplane
- Q: What is the most difficult design challenge you encountered when dealing with backplanes?
- A: In a board, signals travel through an interconnect that consists of board traces, component landing pads, vias, and components. The parasitic capacitance of landing pads and vias introduces impedance mismatch from the characteristic impedance of the board trace. A change in trace width or spacing between a differential pair also creates an impedance mismatch. The difficult part is the placement of components close to the back plane connectors so that I can hide the stub. Managing equal lengths of traces for the LVDS pairs is a challenge as the connector pins are not equispaced. Also the placement of the generator of signal like FPGA is a critical issue. The LVTTL signal traces from the FPGAs have to be short and making that is a challenge. Finally the eye opening and controlling the jitter because of various points mentioned above and the backplane characteristics is a task.
- Q: Is there a better material than FR4 (PCB Material) to improve the high frequency distortion?
- A: Use pcb material with better dielectric constant which is one of the main determinants for higher frequency signal conduction. I am sure the respective pcb house could give you some advice on this area.
- Q: Even though its structure is very simple, backplanes still have a lot of hidden design tricks. What is the best way to approach them without compromising the project?
- A: The backplanes design does not have the simple way, the higher freiquency, the more difficulty. Good chip solution and good PCB design is the best way, I think.
- Q: What is MLVDS?
- A: MLVDS is a LVDS technology designed for multipoint configuration, it is defined in TIA/EIA-889
- Q: Which is best technique for Dc balancing
- A: it depends on the application, for example, 8b/10b encoding scheme is good for byte orientated system but the overhead is 25%. You can simply add a bit to separate a long string of 1's or 0's to achieve DC-balance, for example, National's 24-bit serdes is doing this way
- Q: Are your signal conditioning modules intrinsically safe?
- A: Some of our module has build-in ESD protection.
- Q: How can we fault-proof the backplanes in midst of rising data rates? What are the things we need to remember?
- A: The backplanes are usually bought out items in the design. Very rarely the designers design backplanes. So the designer need to condition the signal before sending it on the backplane and also condition it after receiving it on the Rx end. For LVDS signals which are usually less than 2.5Gbps, the best practice is to use buffers before pushing signal into backplane (stub hiding). Depending on the length of the trace, we can decide on the Pre-emphasis. Also we can implement equilization at the receiving end. If it is a CML signal which are 3Gbps and above, the amplitude is large, close to 1V. Hence we can go for De-emphasis on the Tx side. Other techniques are adaptive equilization and passive equilizers on backplanes etc.
- Q: what type of ckt for emphasis
- A: what is the question?
- Q: Is there evaluation board available to demonstrate the methods mentioned in this talk?
- A: Yes, we have the evaluation board on our website, like equalizer DS38EP100--> http://www.national.com/store/view_item/index.html?nsid=DS38EP100-EVK
- Q: Any request on Power?
- A: Use the information on the recommended operating condition found in the respective data sheet. However, our new passive equalizer do not require power to operate. eg. DS80EP100
- Q: What do you recommend for XAUI interface?
- A: The now-approved XAUI spec specifies a narrow but fast data pipe, which could be deployed using standard CMOS ICs or embedded in ASICs. The spec consists of 4-b streams, each running at 3.125 Gbps, for a total of 12.5 Gbps. Given the 8B/10B encoding/decoding overhead, that's enough to support a 10-Gbps throughput. That speed also matches up with the SONET OC-192 rate of 9.953 Gbps. DS32EL2424 is the serializer we are planning to release to XAUI kind of interfces where the minimum datarate is 3.125Gbps and can reach up to 12.5Gbps toal payload. The above device is a dual device in one pack and we can use 2 such devices to achieve total payload delivery.
- Q: How to decide on the optimum location of the Pre/De emphasis device? If possible, is it OK to place it in the back plane PCB?
- A: buffers are usually placed on the daughter card, located close to the connector so as to (1) hide the stub (2) ESD protect the driving device (3) signal condition the receiving signal before feeding to the receiver devices
- Q: Any request on environment temperature?
- A: The operating environment is like the backplane's. And each chip has its operating temperature, you can check it in the datasheet. Like DS38EP100, its operating temperature is -40ˇăC to +85ˇăC.
- Q: What is the maximum back plane length the National can support now?
- A: it depends on the data rate and the quality of pcb layout, you have to estimate if buffer and EQ are required, case by case
- Q: could pls explain about back plane little bit
- A: The backplane is a PC board (usually passive)which is used to hold several line cards and pass their signals across to other boards. There are various types of backplanes depending on the applications such as PC, Telecom, basestations, etc. Also The back planes will have several layers of traces to accommodate all the signal interconnects. The backplanes are usually characterised in terms of the speed of signal it can handle and hence the cost also is decided.
- Q: Compare to the same products, are there any special characters?
- A: It depend on what kind of product. Like equalizer, the special characters should be max frequency, number of channel, power consumption, active or passive,etc.
- Q: For 10Gbps back plane with 18 Slots, what kind of PCB material you would suggest
- A: for 10Gbps, FR4 is still ok
- Q: Is equalization technique best fit for xDSL application?
- A: It is not sure, depend on the signal quality, frequency and application environment.
- Q: Which scheme you are using for Pre/De emphasis? I mean is it u - law or A - law?
- A: the purpose of pre/de-emphasis is to boost the high freq content of the "data", no specific scheme is required as "distortion" is not critical
- Q: How to counter the cross talk arised from pre/de-emphasis?
- A: pcb layout should be good to reduce the crosstalk due to pre-emphasis, separate two adjacent pairs with sufficient space or put them in different layer
--- 50 Records,Total 3 Page,The 1 Page ---
|