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Q&A
Homepage / Q&A
System Design Make Simple with National's EMI Hardened Amplifiers
- Q: What is the technique element of eliminate noise rejection?
- A: unique hardware filtering.
- Q: What are the bottle-neck problems to improve noise rejection, especially the EMI from the working environment of devices?
- A: The difficulty is for the circuit to distinguish between the noise (the one that down-converted from the EMI) and the wanted signal that is weak (eg. those from a sensor). Next, the frequency range of the noise you trying to avoid. If it is too close to the working band, an external filter would still be needed. National's EMI hardened op. amp. solution offer small,simple and neat solution to address EMI noise issue.
- Q: Which solution is more complicated comparing the traditional techniques with NS techniques?
- A: Hi Eric, NS EMI Hardened Amplifiers is more easier to design, since you do not need add other components as filter like bead, capacitance or active filter, NS solution can solve EMI inside.
Advanced Measurement Techniques for OFDM and MIMO Based Systems
- Q: Please explain what is the algorithm of MIMO?
- A: MIMO allows simultaneous transmission and reception of 2 or more signals. This means that there are 2 or more antennas at the base station and 2 or more antennas at the mobile device.
- Q: What aspects will MIMO and OFDM be applied?
- A: MIMO is being used in WLAN and WiMAX.
- Q: What is Multi-carrier OFDM schemes? How does it work?
- A: OFDMA (Orthogonal Frequency Division Multiple Access). OFDMA is a multiple access transmission technique that uses OFDM modulation techniques. However, individual sets of subcarriers can be assigned to different users so that many users can simultaneously use the channel at the same time. WiMAX dynamically adjusts the allocation of subcarriers, time slots, and bandwidth for optimal throughput for multiple uses. OFDM is the modulation technique used in WiMAX.
Optimize System Performance with FPGA/PCB Co-Design
- Q: How does I/O Designer stay current with the latest FPGA vendor devices?
- A: Mentor Graphics has very strong relationships with the FPGA vendors. There are regular meetings where new device and software plans are exchanged. Based on this information exchange, the I/O Designer team can quickly support new families and devices through software releases or library updates.
- Q: When a device is supported by I/O Designer, does that include pin assignment and swap rules?
- A: Yes. This is called intelligent I/O assignment. I/O Designer allows only legal pin assignments to be made. This is a very powerful capability of I/O Designer that enables I/O optimization. Without this capability, I/O optimization would be very difficult if not impossible.
- Q: What is the difference between pin swapping and I/O optimization?
- A: Good question. Pin swapping requires that swap groups are added to the PCB component and is done in the PCB layout tool. The pin changes are then backannontated to the schematic and then to I/O Designer. I/O optimization is done in I/O Designer and is based on actual PCB layout connectivity. I/O Designer will change pin assignments to remove crossovers and shorten nets. I/O Designer will then update the schematic with the changes.
Maximize Gain & Speed Decompensated Amplifiers
- Q: I want to learn interface of ADc with Philips ARM controller may be 2148 £¬ 669 series £º Texas £º Sigma delta ADC £º
- A: The interface between an ADC and the controller should be in digital form, buffer/amp would normally be use between the sensor/signal-source and the ADC. National has wide ranges of op. amp. meeting various needs.
- Q: What is the meaning of decompensation in amplifiers
- A: Decompensation is the functional deterioration of a previously working structure or system. In Amplifiers, it is a modification of the existing structure to acheive higher bandwidth and safes power. However, this modification makes the amplifier NOT unity gain stable. Therefore, a decompensated amplifier has a minimum gain requirement. If you wished to used the decompensated amplifier below the minimum gain, then you can you the technique introduced in this presentation.
- Q: I couldn't understand how you are calcualating the phase margin from the Gain Vs Frequency graph?
- A: Phase margin was calculated at the point where the 1/F curve and A curve intersects.
Signal Conditioning for Backplane
- Q: What is the most difficult design challenge you encountered when dealing with backplanes?
- A: In a board, signals travel through an interconnect that consists of board traces, component landing pads, vias, and components. The parasitic capacitance of landing pads and vias introduces impedance mismatch from the characteristic impedance of the board trace. A change in trace width or spacing between a differential pair also creates an impedance mismatch. The difficult part is the placement of components close to the back plane connectors so that I can hide the stub. Managing equal lengths of traces for the LVDS pairs is a challenge as the connector pins are not equispaced. Also the placement of the generator of signal like FPGA is a critical issue. The LVTTL signal traces from the FPGAs have to be short and making that is a challenge. Finally the eye opening and controlling the jitter because of various points mentioned above and the backplane characteristics is a task.
- Q: Is there a better material than FR4 (PCB Material) to improve the high frequency distortion?
- A: Use pcb material with better dielectric constant which is one of the main determinants for higher frequency signal conduction. I am sure the respective pcb house could give you some advice on this area.
- Q: Even though its structure is very simple, backplanes still have a lot of hidden design tricks. What is the best way to approach them without compromising the project?
- A: The backplanes design does not have the simple way, the higher freiquency, the more difficulty. Good chip solution and good PCB design is the best way, I think.
Local Oscillator-Characteristics and Design Considerations
- Q: why vco?¡ãs still not digitalized for higher end applications???
- A: DDS, direct digital synthesize has already been widely used
- Q: How can I make a OSC working under a very noisey envierment such as Elec Cuting Machine? T.K.S.
- A: I believe you are refering to electrical signal noise which largely radiated from the machine's electrical noise. eg. large current flow through the cable in the machine. You can consider shielding your OSC circuitry from noise (improve your circuit susceptibility) by mean of metal enclosure, use differential cable/pcb trace whenever possible in your output clock signal path. PCB layout worth pay some attention to minimize cross interference from other nearby circuit. The dc supply to the OSC circuit shall be keep to low noise if possible, the use of low noise LDO is suitable with high PSRR (eg. LP5900)
- Q: What is the frequency range for NSC VCO?
- A: pls visit our website for details, thanks
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