 Q:What is the most difficult design challenge you encountered when dealing with backplanes?
 A:In a board, signals travel through an interconnect that consists of board traces, component landing pads, vias, and components. The parasitic capacitance of landing pads and vias introduces impedance mismatch from the characteristic impedance of the board trace. A change in trace width or spacing between a differential pair also creates an impedance mismatch. The difficult part is the placement of components close to the back plane connectors so that I can hide the stub. Managing equal lengths of traces for the LVDS pairs is a challenge as the connector pins are not equispaced. Also the placement of the generator of signal like FPGA is a critical issue. The LVTTL signal traces from the FPGAs have to be short and making that is a challenge. Finally the eye opening and controlling the jitter because of various points mentioned above and the backplane characteristics is a task.
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